Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a delay locked loop circuit for a semiconductor device.
A synchronous semiconductor device, including a double data rate synchronous dynamic random access memory (DDR SDRAM), transfers data to external devices using an internal clock synchronized with an external clock inputted from an external device.
It is important to synchronize data outputted from a memory cell with an external clock provided by a memory controller to the memory cell in order to stably transfer data between the memory cell and the memory controller.
Herein, the data outputted from the memory cell is synchronized with the internal clock and is outputted. The internal clock is applied to be synchronized with the external clock when the internal clock is applied to the memory cell. However, the internal clock is not synchronized with the external clock when the internal clock is outputted to outside the memory cell because the internal clock is delayed when passing through internal elements of the memory cell.
Accordingly, in order to compensate for the delay and to stably transfer the data outputted from the memory cell, the internal clock should be synchronized with the external clock by adjusting a bus-loading time of the data to correctly align a delayed internal clock with an edge or a center of the external clock. The bus-loading time of the data represents the time for loading data on the bus.
A phase locked loop (PLL) circuit and a delayed locked loop (DLL) are used in a clock synchronization circuit for performing the operation described above.
If a frequency of the external clock and a frequency of the internal clock are different from each other, the PLL is used as the clock synchronization circuit because a frequency dividing function is requested. But, if a frequency of the external clock is identical to a frequency of the internal clock, the DLL is used as the clock synchronization circuit because the DLL is implemented in a smaller area than the PLL and is not as sensitive to a noise as the PLL.
Because the semiconductor device uses the same frequency, the DLL is widely used as the clock synchronization circuit.
In particular, a register controlled DLL is most widely used in the semiconductor device.
The register controlled DLL has a register for storing a locked delay value. The register controlled DLL performs a clock synchronization operation at a relatively small phase difference between the internal clock and the external clock in an initial operation of a semiconductor device by storing the locked delay value in the register when a power is switched off, and by loading the locked delay value stored in the register to lock the internal clock when the power is applied to the memory device. After the initial operation of the semiconductor device, the register controlled DLL may decrease a time consumed in the synchronization of the internal clock and the external clock by adjusting a variation width of the locked delay value of the register based on a phase difference between the internal clock and the external clock.
FIG. 1 is a block diagram illustrating a register controlled DLL circuit in accordance with a conventional semiconductor device.
As shown in FIG. 1, a register controlled DLL circuit in accordance with a conventional semiconductor device includes a clock buffering unit 180, a phase comparison unit 100, a clock delay unit 120, a delay locked clock generating unit 140 and a delay replica model unit 160.
The clock buffering unit 180 receives an external clock CLK and an inverted clock CLK# of the external clock (hereinafter, referred to as an inverted external clock CLK#) inputted from an external device. The clock buffering unit 180 outputs a reference clock REFCLK to the phase comparison unit 100, and outputs a first reference clock REFCLK_F and a second reference clock REFCLK_R to the clock delay unit 120.
The clock comparison unit 100 receives the reference clock REFCLK and a feedback clock FBCLK, compares the reference clock REFCLK with the feedback clock FBCLK, and generates first and second delay control signals DLY_LOCK_CRL_F and DLY_LOCK_CRL_R.
The clock comparison unit 100 includes a clock phase comparison block 102 and a delay control signal generating block 104.
The clock phase comparison block 102 compares a phase of the reference clock REFCLK with a phase of the feedback clock FBCLK and generates a clock comparison signal PHASE_COMP.
The delay control signal generating block 104 generates the first delay control signal DLY_LOCK_CRL_F for controlling a delay operation of to a first clock delay block 122 of the clock delay unit 120 in response to the clock phase comparison signal PHASE_COMP, and generates the second delay control signal DLY_LOCK_CRL_R for controlling a delay operation of a second clock delay block 124 of the clock delay unit 120 in response to the clock phase comparison signal PHASE_COMP.
The clock delay unit 120 delays the first and second reference clocks REFCLK_F and REFCLK_R corresponding to first and second edges (e.g., a falling edge and a rising edge) of the reference clock in response to the first and second delay control signals DLY_LOCK_CRL_F and DLY_LOCK_CRL_R, respectively, and outputs first and second delay locked clocks DLLCLK_F and DLLCLK_R as delayed clocks of the first and second reference clocks REFCLK_F and REFCLK_R, respectively.
The clock delay unit 120 includes the first clock delay block 122 and the second clock delay block 124.
The first clock delay block 122 delays the first reference clock REFCLK_F by a delay amount corresponding to the first delay control signal DLY_LOCK_CRL_F outputted from the phase comparison unit 100, and outputs the first delay locked clock DLLCLK_F as the delayed clock of the first reference clock REFCLK_F.
The second clock delay block 124 delays the second reference clock REFCLK_R by a delay amount corresponding to the second delay control signal DLY_LOCK_CRL_R outputted from the phase comparison unit 100, and outputs the second delay locked clock DLLCLK_R as the delayed clock of the second reference clock REFCLK_R.
The delay locked clock generating unit 140 mixes a phase of the first delay locked clock DLLCLK_F and a phase of the second delay locked clock DLLCLK_R, and outputs a delay locked clock DLLCLK as a phase-mixed clock of the first and second delay locked clock DLLCLK_F and DLLCLK_R.
The delay replica model unit 160 reflects a delay time of a real output path of the reference clock REFCLK on the delay locked clock DLLCLK, and outputs the feedback clock FBCLK.
A basic locking operation of the register controlled DLL circuit in accordance with the conventional semiconductor device is described immediately below.
The first delay locked clock DLLCLK_F and the second delay locked clock DLLCLK_R are outputted by delaying the first reference clock REFCLK_F corresponding to a first edge of the reference clock REFCLK and the second reference clock REFCLK_R corresponding to a second edge of the reference clock REFCLK, respectively, in order to synchronize a rising edge of the reference clock REFCLK with a rising edge of the feedback clock FBCLK having a different phase before the locking state.
Herein, a phase of the first delay locked clock DLLCLK_F is mixed with a phase of the second delay locked clock DLLCLK_R to generate a delay locked clock DLLCLK. A real delay condition of the reference clock REFCLK is reflected on the delay locked clock DLLCLK, and the feedback clock FBCLK is outputted. As a phase delay amount of the first reference clock REFCLK_F and the second reference clock REFCLK_R increases, a phase difference between the reference clock REFCLK and the feedback clock FBCLK decreases.
Meanwhile, the clock delay unit 120 described above is configured to prevent a distortion of a duty ratio of the delay locked clock DLLCLK outputted from a DLL circuit.
In the case of an external clock CLK and an inverted external clock CLK# inputted from an external device, a distorted duty ratio may be inputted and a delay locked clock DLLCLK may have the distorted duty ratio when a delay locked operation is simply performed with the external clock CLK and the inverted external clock CLK#.
However, distortion of the duty ratio of the delay locked clock DLLCLK outputted from the DLL circuit is prevented by the DLL circuit as shown in FIG. 1.
When the external clock CLK and the inverted external clock CLK# have high frequencies, the duty ratio correction operation is requested. However, when the external clock CLK and the inverted external clock CLK# have low frequencies, the duty ratio correction operation is not requested.
That is, when the external clock CLK and the inverted external clock CLK# have high frequencies, the distortion of the duty ratio may cause a large jitter because one period of a clock is very short. However, when the external clock CLK and the inverted external clock CLK# have low frequencies, the distortion of the duty ratio may cause little jitter because one period of a clock is very long.
Further, when the external clock CLK and the inverted external clock CLK# have high frequencies, a delay amount of a clock delay unit, compensated according to a phase difference between the reference clock REFCLK and the feedback clock FBCLK, is very short because one period of a clock is very short. However, when the external clock CLK and the inverted external clock CLK# have low frequencies, a delay amount of a clock delay unit, compensated according to a phase difference between the reference clock REFCLK and the feedback clock FBCLK, is very long because one period of a clock is very long.
Accordingly, because the register controlled DLL circuit in accordance with the conventional semiconductor device performs a duty ratio correction operation irrespective of the frequencies of the external clock CLK and the inverted external clock CLK#, the operation of the register controlled DLL circuit is inefficient, and the clock delay unit must have a large area to generate a large delay amount for outputting the delay locked clock DLLCLK.